BRN Discussion Ongoing

[7für7]

@perceptron

But to give you a answer which is more accurate… and maybe you can tell us your results later? We would be thankful

Manufacturing “variable costs” for a silicon chip (e.g., BrainChip’s Akida AKD2500 in a fabless model) are not a single line item — you have to separate true per-unit variable costs from volume-driven/step costs and non-recurring costs that still have to be amortized if you want real unit economics.

1) True variable manufacturing costs (scale with each unit shipped)

A) Foundry / Wafer cost

• Price per wafer (depends on node, wafer size, foundry, volume tiers, contract terms)
• Wafer probe / E-test (often priced per wafer or per die)

To convert wafer cost into cost per good die, you need:

• Wafer price
• Gross dies per wafer (depends on die area + wafer geometry)
• Wafer yield (good dies / gross dies)

Rule of thumb formula:

Cost_per_good_die ≈ Wafer_cost / (Gross_dies_per_wafer × Yield)

B) Assembly / Packaging (OSAT)

• Package type (QFN/BGA/WLCSP, etc.), pin/ball count, substrate/leadframe, thermal/reliability requirements
• Typically quoted as cost per packaged unit, but strongly volume-tiered

C) Final test / QA

• ATE test time and coverage (test time is often the big driver)
• Burn-in / stress test if required
• Sampling, screening, and quality checks (some per-unit, some batch/step)

D) Backend handling & losses

• Marking (laser), tape-and-reel, handling
• Scrap / rework / backend yield loss (assembly yield is separate from wafer yield)

E) Logistics to make a deliverable unit

• Freight between foundry → OSAT → distribution
• Duties, insurance, warehousing/handling (often ignored in “manufacturing” discussions, but it’s still per-unit/volume-linked if you’re doing landed unit cost)

2) Other costs “associated with producing chips” (not clean per-unit, but volume matters)

A) NRE (non-recurring engineering) / mask costs

Not variable per chip, but you must amortize it to understand economics:

• Mask set, tapeout, sign-off, engineering runs

Amortized NRE per unit:

Amortized_NRE_per_unit = Total_NRE / Lifetime_units

B) EDA + IP licensing

• Tooling and IP block licenses (mostly fixed/periodic)
• Sometimes running royalties depending on the deal structure

C) Test program development, validation, customer enablement

• Test program creation, characterization, reliability quals
• Reference designs, support, and variant management (grows with customers/SKUs)

D) “Step costs” at higher volume

• Extra test capacity, QA/reliability lots, supply-chain headcount
  These don’t scale perfectly linearly; they jump at volume thresholds.

3) Fabless reality check (relevant for Akida AKD2500)

BrainChip (fabless) typically pays:

• Foundry wafer costs

• OSAT assembly + test
• Logistics/distribution
• Plus NRE/EDA/IP and ongoing engineering/support

They do not carry the capex/opex of owning a wafer fab, but that doesn’t make “manufacturing cost” simple — it just shifts the cost structure into supplier pricing + yields + test time + volume tiers.

If you want to actually calculate a per-chip cost
You need (at minimum):

1. Wafer cost (with volume tier)
2. Die area → gross dies/wafer
3. Wafer yield (%)
4. Package/assembly cost per unit
5. Final test cost per unit (ATE time, multisite, coverage)
6. Backend yield (%)
7. Freight/duty/handling per unit (or per batch)
8. Total NRE + expected lifetime units (for amortization)

Without those inputs (especially die size, yields, package type, test time, and volume pricing), any single “cost per chip” number is just guessing.

Hope this helps!

 

[perceptron]

Morning Perceptron ,

I'm still grappling with the discrepancy in global banana prices...

America, up to US$3,800,000 per Banana.

Australia, roughly AU$6.00 per KG , ( about AU$1.79 per fruit ).

OBVIOUSLY it's hard to extrapolate how many bananas are consumed by all the diffrent workers in diffrent fields in diffrent countries .

And this is but one possible input cost , rather hard to put an exact cost per chip , until all the knowen knowens & the unknowen unknowens are knowen .

Hope this helps.

Regards,
Esq.

So a simple research question/discussion is not one of your strengths.

 

[perceptron]

@perceptron

But to give you a answer which is more accurate… and maybe you can tell us your results later? We would be thankful

Manufacturing “variable costs” for a silicon chip (e.g., BrainChip’s Akida AKD2500 in a fabless model) are not a single line item — you have to separate true per-unit variable costs from volume-driven/step costs and non-recurring costs that still have to be amortized if you want real unit economics.

1) True variable manufacturing costs (scale with each unit shipped)

A) Foundry / Wafer cost

• Price per wafer (depends on node, wafer size, foundry, volume tiers, contract terms)
• Wafer probe / E-test (often priced per wafer or per die)

To convert wafer cost into cost per good die, you need:

• Wafer price
• Gross dies per wafer (depends on die area + wafer geometry)
• Wafer yield (good dies / gross dies)

Rule of thumb formula:

Cost_per_good_die ≈ Wafer_cost / (Gross_dies_per_wafer × Yield)

B) Assembly / Packaging (OSAT)

• Package type (QFN/BGA/WLCSP, etc.), pin/ball count, substrate/leadframe, thermal/reliability requirements
• Typically quoted as cost per packaged unit, but strongly volume-tiered

C) Final test / QA

• ATE test time and coverage (test time is often the big driver)
• Burn-in / stress test if required
• Sampling, screening, and quality checks (some per-unit, some batch/step)

D) Backend handling & losses

• Marking (laser), tape-and-reel, handling
• Scrap / rework / backend yield loss (assembly yield is separate from wafer yield)

E) Logistics to make a deliverable unit

• Freight between foundry → OSAT → distribution
• Duties, insurance, warehousing/handling (often ignored in “manufacturing” discussions, but it’s still per-unit/volume-linked if you’re doing landed unit cost)

2) Other costs “associated with producing chips” (not clean per-unit, but volume matters)

A) NRE (non-recurring engineering) / mask costs

Not variable per chip, but you must amortize it to understand economics:

• Mask set, tapeout, sign-off, engineering runs

Amortized NRE per unit:

Amortized_NRE_per_unit = Total_NRE / Lifetime_units

B) EDA + IP licensing

• Tooling and IP block licenses (mostly fixed/periodic)
• Sometimes running royalties depending on the deal structure

C) Test program development, validation, customer enablement

• Test program creation, characterization, reliability quals
• Reference designs, support, and variant management (grows with customers/SKUs)

D) “Step costs” at higher volume

• Extra test capacity, QA/reliability lots, supply-chain headcount
  These don’t scale perfectly linearly; they jump at volume thresholds.

3) Fabless reality check (relevant for Akida AKD2500)

BrainChip (fabless) typically pays:

• Foundry wafer costs

• OSAT assembly + test
• Logistics/distribution
• Plus NRE/EDA/IP and ongoing engineering/support

They do not carry the capex/opex of owning a wafer fab, but that doesn’t make “manufacturing cost” simple — it just shifts the cost structure into supplier pricing + yields + test time + volume tiers.

If you want to actually calculate a per-chip cost
You need (at minimum):

1. Wafer cost (with volume tier)
2. Die area → gross dies/wafer
3. Wafer yield (%)
4. Package/assembly cost per unit
5. Final test cost per unit (ATE time, multisite, coverage)
6. Backend yield (%)
7. Freight/duty/handling per unit (or per batch)
8. Total NRE + expected lifetime units (for amortization)

Without those inputs (especially die size, yields, package type, test time, and volume pricing), any single “cost per chip” number is just guessing.

Hope this helps!

So you are saying that cost per chip relates to manufacture costs and that variable costs are added? You have used ADK2500 here, the original discussion was in relation to ADK1500 capital raise November 2025, page 14, titled "Path to commercialisation - Product ADK1500". Further, the question was "what are the variable costs in manufacturing a silicon chip and are there any other costs associated with manufacturing silicon chips".

 

[7für7]

So you are saying that cost per chip relates to manufacture costs and that variable costs are added? You have used ADK2500 here, the original discussion was in relation to ADK1500 capital raise November 2025, page 14, titled "Path to commercialisation - Product ADK1500". Further, the question was "what are the variable costs in manufacturing a silicon chip and are there any other costs associated with manufacturing silicon chips".

Yes …in general “cost per chip” refers to unit manufacturing cost (COGS per unit), which is mainly variable per shipped unit, and sometimes people also allocate/amortise fixed or one-off costs into a “per-chip” number depending on the model.

And you’re right to call it out: the discussion was about ADK1500 (Capital Raise Nov 2025, page 14: “Path to commercialisation – Product ADK1500”) — so referencing ADK2500 was off-target for that specific question, even if the cost logic is similar across products.

What are the variable costs in manufacturing a silicon chip?

Typical variable per-unit costs include:
1. Foundry wafer cost (per wafer)
Often the biggest component. Unit economics are driven by:
Cost per good die = wafer price / (dies per wafer × yield)
2. Packaging / assembly
Package type, substrate (if needed), bonding/flip-chip, underfill, etc.
3. Test costs
Wafer sort + final test; tester time can be expensive and scales with complexity/test time.
4. Final QA / handling
Marking, inspection, bake, tape & reel/trays, etc.
5. Logistics per unit
Packing, shipping, customs/handling depending on the supply chain.

Yield is the big lever: poorer yield = higher cost per good chip.

Are there other costs associated with manufacturing silicon chips?

Yes — commonly overlooked “manufacturing-associated” costs that are not purely variable per unit:
• NRE / one-off costs: mask set/reticles, tape-out, DFT, verification, IP licensing, packaging tooling, qualification & characterisation.
These aren’t per unit, but companies often amortise them into a per-chip model.
• Fixed/periodic manufacturing support costs: operations/quality engineering, supplier management, failure analysis, RMA/returns handling, etc.
• Inventory & scrap risks: write-downs, obsolescence, scrap/rework — not always variable, but very real in practice.

So…
Variable chip manufacturing costs = wafer + yield impact + packaging + test + unit logistics. Other associated costs = masks/NRE + qualification + manufacturing support + scrap/returns/inventory risks (often fixed or amortised).

 

[White Horse]

Just checking to see how everyone went their research topic: "What are the variable costs in manufacturing silicon chips and are there other costs associated when producing silicon chips?"

Oh! Fuck Off. !!!

 

[HopalongPetrovski]

No, that variable costing was clearly stated in the metrics. Interestingly, the following metric is the price/chip (volume dependent) of $4 - $50.

Ok. So you are not concerned about the $2.94 amount.
What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?
As per usual practice, a buyer gets an effective discount when ordering in bulk.
eg....if you order 10, the price is $50 each.
if you order 10,000, the price is $4 each.
What is your issue with this?

 

[perceptron]

Yes …in general “cost per chip” refers to unit manufacturing cost (COGS per unit), which is mainly variable per shipped unit, and sometimes people also allocate/amortise fixed or one-off costs into a “per-chip” number depending on the model.

And you’re right to call it out: the discussion was about ADK1500 (Capital Raise Nov 2025, page 14: “Path to commercialisation – Product ADK1500”) — so referencing ADK2500 was off-target for that specific question, even if the cost logic is similar across products.

What are the variable costs in manufacturing a silicon chip?

Typical variable per-unit costs include:
1. Foundry wafer cost (per wafer)
Often the biggest component. Unit economics are driven by:
Cost per good die = wafer price / (dies per wafer × yield)
2. Packaging / assembly
Package type, substrate (if needed), bonding/flip-chip, underfill, etc.
3. Test costs
Wafer sort + final test; tester time can be expensive and scales with complexity/test time.
4. Final QA / handling
Marking, inspection, bake, tape & reel/trays, etc.
5. Logistics per unit
Packing, shipping, customs/handling depending on the supply chain.

Yield is the big lever: poorer yield = higher cost per good chip.

Are there other costs associated with manufacturing silicon chips?

Yes — commonly overlooked “manufacturing-associated” costs that are not purely variable per unit:
• NRE / one-off costs: mask set/reticles, tape-out, DFT, verification, IP licensing, packaging tooling, qualification & characterisation.
These aren’t per unit, but companies often amortise them into a per-chip model.
• Fixed/periodic manufacturing support costs: operations/quality engineering, supplier management, failure analysis, RMA/returns handling, etc.
• Inventory & scrap risks: write-downs, obsolescence, scrap/rework — not always variable, but very real in practice.

So…
Variable chip manufacturing costs = wafer + yield impact + packaging + test + unit logistics. Other associated costs = masks/NRE + qualification + manufacturing support + scrap/returns/inventory risks (often fixed or amortised).

So the price/chip (volume dependent) is added to the variable costs? That would mean the price to end user (final customer of the IP/Chip designer) is unknown until revenue is announced?

 

[perceptron]

Ok. So you are not concerned about the $2.94 amount.
What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?
As per usual practice, a buyer gets an effective discount when ordering in bulk.
eg....if you order 10, the price is $50 each.
if you order 10,000, the price is $4 each.
What is your issue with this?

1. "What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?"
Where on page 14 is there wording that suggests your statement to be true?
2. "What is your issue with this?"
Please refer to point 1.

 

[7für7]

Ok. So you are not concerned about the $2.94 amount.
What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?
As per usual practice, a buyer gets an effective discount when ordering in bulk.
eg....if you order 10, the price is $50 each.
if you order 10,000, the price is $4 each.
What is your issue with this?

He is just trolling… if he wants to know, he should be able to research by himself and calculate it… we are not his employees to bring numbers to the table… he also is free to call the headquarter or writing an email to get a proper answer…. He is just a bored person who needs some attention… who cares about the costs? We can not control them anyway… the only thing we can do is see what they can sell waiting for announcements and quarterly reports and watch them NOW!

Only my opinion …DYOR

 

[7für7]

So the price/chip (volume dependent) is added to the variable costs? That would mean the price to end user (final customer of the IP/Chip designer) is unknown until revenue is announced?

So, the price/chip (volume dependent) is added to the variable costs! That means the price to end user (final customer of the IP/Chip designer) is unknown until revenue is announced!

 

[Bravo]

So the price/chip (volume dependent) is added to the variable costs? That would mean the price to end user (final customer of the IP/Chip designer) is unknown until revenue is announced?

OMG! You're really doing my head in!

You have been asked politely COUNTLESS times to stop being so cryptic and simply articulate your point instead of expecting us all to be psychics who can read your mind.

We get it that fabs don’t run on vibes and sausage sizzles to get by.

Yes, there are fixed costs. Yes, there are overheads. Yes, wafers don’t grow on trees.

But unless you’re suggesting the per-unit cost is actually $15 or $25 instead of $2.94, maybe just say that !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

You keep circling the runway without actually landing the plane.

What’s your actual number (if you even have one)?

Land the plane, mate!

 

[HopalongPetrovski]

1. "What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?"
Where on page 14 is there wording that suggests your statement to be true?
2. "What is your issue with this?"
Please refer to point 1.

Where on page 14 is there wording that suggests your statement to be true?

It states it clearly in the graphic.

Price/chip (volume dependent)
The Price per chip is volume dependent.

 

[Food4 thought]

Morning Perceptron ,

I'm still grappling with the discrepancy in global banana prices...

America, up to US$3,800,000 per Banana.

Australia, roughly AU$6.00 per KG , ( about AU$1.79 per fruit ).

OBVIOUSLY it's hard to extrapolate how many bananas are consumed by all the diffrent workers in diffrent fields in diffrent countries .

And this is but one possible input cost , rather hard to put an exact cost per chip , until all the knowen knowens & the unknowen unknowens are knowen .

Hope this helps.

Regards,
Esq.

Banana chips

 

[IloveLamp]

#starlinkd2c #directtocell #reinforcementlearning #spacexakida #neuromorphicai #brazildigitalinclusion #satelliteedgecomputing #leoinnovation #spacex #akida #starlink #d2c | Daniel Azevedo Novais

✨ ⚙️ Starlink Direct‑to‑Cell: RL‑Driven Autonomous Beam Management for Remote Brazil The objective is to maximize population coverage and spectral efficiency in critical regions including the Legal Amazon, Pantanal wetlands, and the Northeastern backlands. As of February 2026, Starlink...

www.linkedin.com

 

[7für7]

#starlinkd2c #directtocell #reinforcementlearning #spacexakida #neuromorphicai #brazildigitalinclusion #satelliteedgecomputing #leoinnovation #spacex #akida #starlink #d2c | Daniel Azevedo Novais

✨ ⚙️ Starlink Direct‑to‑Cell: RL‑Driven Autonomous Beam Management for Remote Brazil The objective is to maximize population coverage and spectral efficiency in critical regions including the Legal Amazon, Pantanal wetlands, and the Northeastern backlands. As of February 2026, Starlink...

www.linkedin.com

View attachment 95378 View attachment 95379 View attachment 95380

I don’t know why there are recently popping up this guys with AI generated material without sources to validate the information…. It’s kind of agenda? Paid from who to misleading people? I don’t get it…

 

[Food4 thought]

Ok. So you are not concerned about the $2.94 amount.
What exactly don't you understand about BrainChip stating they will sell for $4 - $50 depending on the amount of volume ordered?
As per usual practice, a buyer gets an effective discount when ordering in bulk.
eg....if you order 10, the price is $50 each.
if you order 10,000, the price is $4 each.
What is your issue with this?

It’s like anything that you buy
Volume gives you room to move
In any manufacturing the more you purchase the better deal you can get
It’s a win win
Also the better it is for everyone from the production level down to the buyer at the shop.
I don’t see the point of the discussion.

 

[Jacob Kiraz]

This Page is just a research linking page with the hope of something,
What a disgrace its all crap this NDA'S, Whats a NDA when its not in a product , for 5 years if not more there been throwing these lines out
Companies can throw that line out all day its time shine and get information out there if companies are with us or not and akida is in any product,
Im sick of hearing garbage and the IBM Line is a classic, mercedes , toyota, and there is many more, why haant anything come thru

 

[7für7]

This Page is just a research linking page with the hope of something,
What a disgrace its all crap this NDA'S, Whats a NDA when its not in a product , for 5 years if not more there been throwing these lines out
Companies can throw that line out all day its time shine and get information out there if companies are with us or not and akida is in any product,
Im sick of hearing garbage and the IBM Line is a classic, mercedes , toyota, and there is many more, why haant anything come thru

Because of the NDAs

 

[perceptron]

It’s like anything that you buy
Volume gives you room to move
In any manufacturing the more you purchase the better deal you can get
It’s a win win
Also the better it is for everyone from the production level down to the buyer at the shop.
I don’t see the point of the discussion.

The logic and the mathematics in relation to the metrics provided and interpreted (by some here) makes no business sense. Do Hoppy's interpretation of the metrics after researching variable costs to manufacture a silicon chip and research if there are other costs associated with manufacturing silicon chips that a foundry, not the IP/Chip designer has to factor in when pricing their production costs. It's well worth the effort.

 

[7für7]

The logic and the mathematics in relation to the metrics provided and interpreted (by some here) makes no business sense. Do Hoppy's interpretation of the metrics after researching variable costs to manufacture a silicon chip and research if there are other costs associated with manufacturing silicon chips that a foundry, not the IP/Chip designer has to factor in when pricing their production costs. It's well worth the effort.

I always find it funny when people try to sound “smart” by throwing around jargon instead of delivering actual substance and ignoring detailed answers…

And since you keep coming back with follow-up questions, it honestly looks like you haven’t understood the basic principle yet.

So let’s start right at the beginning: addition and subtraction. We’ve got a long road ahead.
And before you ask how I know when to use which one…first learn how to pronounce those two words properly. Then we’ll continue.