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“Our final webinar of the year in the AI Hardware Summit series takes place next Tuesday (Dec 20) from 10am PT, and will be hosted by the Senior Manager, Applications Engineering and Senior ASIC Digital Design Engineer at Synopsys.
Register for free here
This webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions.
Full webinar abstract and free registration here!
“Our final webinar of the year in the AI Hardware Summit series takes place next Tuesday (Dec 20) from 10am PT, and will be hosted by the Senior Manager, Applications Engineering and Senior ASIC Digital Design Engineer at Synopsys.
Register for free here
This webinar will introduce the Synopsys ARC® NPX Neural Processing Unit (NPU) IP family of embedded AI processors and use of Synopsys VC Formal DPV to verify its datapath functions.
Full webinar abstract and free registration here!