Hi Fmf,@diogene
@Diogenese
You may have done previously and I missed or maybe haven't.
Could you run your eye over?
Bit above my pay grade
View attachment 25056
Whilst this recent Qualcomm patent app is around neuromorphic processing, patents are always so open ended in some areas (for good reason I get that), so becomes grey sometimes when skimming.
They discuss DCN (deep convolutional) and not SNN and feedforward but then also backprop and feedback (top down) methods albeit not being as efficient as I read it?
Looks like 3d stack fab obviously.
Can be on ARM instruction set architecture, ASIC, DSP and FPGA etc.
Things get left open a bit and wondered if our IP has a space in here at all on converting DCN to SNN which I suspect wouldn't get a mention in a patent like this or whether it's not viable?
TIA
Specification paper lodged attached.
WIPO - Search International and National Patent Collections
patentscope.wipo.int
This patent has nothing to do with Akida. As you said, it is about the physical 3D layout of an array of near-memory NPU cores. They save power by jiggling the supply voltage to the cores.
WO2019046835A1 ULTRA-LOW POWER NEUROMORPHIC ARTIFICIAL INTELLIGENCE COMPUTING ACCELERATOR
[0008] A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.
[0062] The homogenous configuration may be implemented in the local power manager 740 using a power management integrated circuit (PMIC). In this configuration, the local power manager may be fabricated using an ultra-low voltage process, such as a fully depleted (FD)-semiconductor-on-insulator (FD-SOI) wafer process, or other ultra-low voltage process. The local power manager 740 may be configured to perform snoops on adjacent cores using, for example, handshaking circuity to communicate core-to-core to decide the power state of a corresponding core.
[0063] In one aspect of the present disclosure, the local power manager 740 may be configured to provide adaptive voltage scaling to enable sub-threshold voltage (e.g., 0.2 V to 0.25 V) operation. In this configuration, smart power management is provided by including a global power manager (GPM) 710 to coordinate with each local power manager 740 to provide dynamic voltage frequency scaling (DVFS) and power collapse control for each tier 702. In aspects of the present disclosure, the GPM 710 (shown off- chip) can be either on-chip or off-chip. In this example, the GPM 710 delivers power to a set of cores (e.g., the cores on one tier or multiple tiers), whereas the local power manager 740 derives power for each individual core.