BRN Discussion Ongoing

[Fullmoonfever]

Know my last couple of posts banging on about FDSOI but I'm curious to understand the shift by BRN for AKD1500.

As suggested prev, possible input from potential / existing clients as an option / POC?

Another random thought....does 1500 use a little more power and as such shifting to FDSOI assists keeping low power as it's less hungry?

One other after reading the below, is if it's also strategic. With GF coming online in France in a couple years it gives Euro clients the capability / option of using them locally from a supply chain view increasing Akida access / footprint?

STMicroelectronics and GlobalFoundries Jointly Press on with FD-SOI in a New Fab Near Grenoble

STMicroelectronics (ST) and GlobalFoundries (GF) have just signed a memorandum of understanding to create a new, jointly operated 300mm semiconductor fab to be located alongside ST’s existing fab i…

www.eejournal.com

August 1, 2022

STMicroelectronics and GlobalFoundries Jointly Press on with FD-SOI in a New Fab Near Grenoble​

by Steven Leibson
STMicroelectronics (ST) and GlobalFoundries (GF) have just signed a memorandum of understanding to create a new, jointly operated 300mm semiconductor fab to be located alongside ST’s existing fab in Crolles, France. The new fab will support multiple semiconductor technologies and process nodes, including FD-SOI (fully depleted silicon on insulator). ST and GF expect that the fab will start producing chips in 2024 and will ramp to full capacity, producing as many as 620,000 300mm wafers per year, by 2026.
The Grenoble area in southeastern France, not far from the Italian border, has long been a hotbed of FD-SOI development. In many ways, FD-SOI is a lower-tech approach to realizing some of the benefits of FinFETs and gate-all-around FETs (GAAFETs) – including higher speed, lower power consumption, and less parametric variation on a chip from transistor to transistor thanks to the conduction channel being fully depleted (undoped). Less on-chip parametric variation means that IC designers can reduce the amount of design margin needed – for both supply voltage and timing – which improves the chip’s speed and lowers its power consumption by lowering the required operating voltage.
Dr. Chenming Hu and his team at the University of California, Berkeley, developed FinFETs way back in 1999 under a DARPA contract. DARPA cut that contract because it was clear that planar FETs would eventually run out of gas after their half-century run as they were scaled smaller and smaller. DARPA sought an alternative.
Small planar FETs suffer from short-channel leakage, which prevents the FET from turning off completely. The advantage that FinFETs have over planar FETs is that the FinFET architecture constructs a gate around three of the FET channel’s four sides. This arrangement allows the electric field from the gate to penetrate more deeply into the FET’s conduction channel, which reduces short-channel leakage and allows better control over the current through the channel.
Short-channel leakage increased in magnitude as planar FET dimensions shrunk, causing power consumption and heat-dissipation challenges to grow and forcing semiconductor makers to adopt FinFETs. Intel was the first commercial semiconductor company to adopt FinFETs for its 22nm process node back in 2011, more than a decade after FinFETs were first developed. FinFETs are currently used almost universally for chips made with 20nm process nodes or newer.
However, FinFETs are now running out of gas. Driving three sides of the FinFET transistor’s gate no longer achieves the desired speeds and low leakage currents. We must now drive all four sides of the FET gate to get a well-behaved transistor. Enter GAAFETs, which are already in production at Samsung’s fabs in that company’s 3nm process node. Intel and TSMC will also be using GAAFETs for their Intel 20A and N2 2nm nodes respectively. Samsung calls its GAAFETs “Multi-Bridge-Channel FETs” (MBCFETs); Intel calls them “RibbonFETs”; and TSMC calls them nanosheet GAAFETs. (See “Intel Welcomes You to the Angstrom Era” and “Moore’s Law: Not Dead Yet? Nope, Says Intel:, Behold Intel 4… and 3.”)
Like FinFETs, GAAFETs are 3D structures. Instead of fins, GAAFET conduction channels are built with undoped silicon nanowires, nanosheets, or ribbons that are so thin that they are essentially 2D structures, made with advanced process technologies such as atomic layer deposition (ALD). These nanoscale conduction channels are entirely encapsulated by the GAAFET’s gate structure.

​

The ultra-thin conduction channel of an FD-SOI FET does not suffer from the same leakage effects as a planar FET made in bulk silicon. Image credit: STMicroelectronics.
FD-SOI FETs have what is essentially a 2D conduction channel, created by bonding or otherwise applying a very thin, extremely uniform layer of silicon on top of a thin, grown silicon dioxide insulation layer. If the FD-SOI FET’s conduction channel is thin enough, the electric field from the transistor gate sitting on top of the conduction channel fully penetrates the channel, thus eliminating the need for a gate structure that surrounds the channel on all four sides, as is done with GAAFETs.
Except for the FD-SOI substrate, FD-SOI FETs are made in a similar manner and with the same equipment used to make planar FETs. The GAA structure is more complex and requires the use of expensive EUV lithography to create the small structures required. Like FinFETs and GAAFETs, FD-SOI FETs do not suffer from short-channel leakage problems, and they don’t require EUV lithography as do GAAFETs. So, you might call FD-SOI transistors “gate-almost-all-around FETs” (GAAAFETs). You might, but no one does.
By an interesting coincidence, the same UC Berkeley team – led by Dr. Chenming Hu – that developed the FinFET under a DARPA contract in 1999, simultaneously developed something very much akin to the FD-SOI FET architecture under the very same DARPA contract. Hu dubbed this second FET structure UTBSOI (Ultra Thin Body Silicon on Insulator).
FinFETs, GAAFETs, and UTBSOI FETs offer many benefits over planar MOSFETs:

• Better signal swing
• Less sensitivity to gate length and drain voltage
• No random dopant fluctuations because the FinFETs fins, the nanostructured conduction channels in GAAFETs, and the thin conduction channel in UTBSOI/FD-SOI FETs are all fully depleted – they’re not doped
• Higher on current with lower leakage
• Lower Vdd and lower leakage, therefore less power consumption

There are at least two important differences between FinFETs or GAAFETs and UTBSOI/FD-SOI FETs. First, it’s relatively easy to add back biasing beneath the channel of an FD-SOI FET, a capability that’s enabled by the bulk silicon substrate under the thin insulating layer on the wafer. Back biasing allows you to play with FET threshold voltages and to tweak performance and power consumption. If you decide to get really fancy, you can tweak individual FETs on the chip by using the silicon under each transistor as a second gate. There’s no easy way to add back biasing to FinFETs or GAAFETs. Second, you don’t get smaller transistors with FD-SOI relative to FinFETs or GAAFETs, so you don’t achieve the same transistor densities. That’s the flip side of not requiring expensive EUV lithography.
FD-SOI processing is still more expensive than conventional planar IC processing because it requires special FD-SOI wafers. It’s just not as expensive as the EUV lithography and other 3D processing techniques needed to make small FinFETs and GAAFETs. Conventional IC manufacturing uses bulk silicon wafers, which are much less expensive than FD-SOI wafers. The major supplier of FD-SOI wafers is Soitec in Bernin, which is literally just down the street from the STMicroelectronics Crolles fab complex north of Grenoble.

​

By coincidence, Soitec, GF, and ST, along with CEA (the French Alternative Energies and Atomic Energy Commission), announced a collaborative agreement earlier this year to jointly define the industry’s next generation roadmap for FD-SOI. In that announcement, CEA Chairman François Jacq said, “CEA has… a long history of deep R&D cooperation with… STMicroelectronics, Soitec and GlobalFoundries and has been very active in the initiatives led by the European Commission and Member States aiming to set up a complete ecosystem for FD-SOI going from material suppliers, design houses, EDA tools providers, fabless companies, and end users.” These are the elements that constitute an FD-SOI “platform.”
July’s ST/GF FD-SOI memorandum announcement also says, “ST and GF will receive significant financial support from the State of France for the new facility. This facility will strongly contribute to the objectives of the European Chips Act, including the goal of Europe reaching 20% of worldwide semiconductor production by 2030.” This statement was a European poke in the eye for the US government, which appeared to be dragging its heels on the country’s own CHIPS Act, much to the chagrin of companies such as Intel and TSMC. However, the US Senate and House of Representatives finally passed the bill last week and US President Joe Biden is expected to sign it into law this week.
It appears that France is going big on FD-SOI, which is not a bad strategy if you don’t plan to buy a $150 million EUV stepper or the next-generation $300 million “High NA” EUV stepper from ASML. FD-SOI confers many of the FinFET’s and GAAFET’s advantages on a far less expensive process node. GF already offers two FD-SOI process nodes or platforms called RF SOI and 22nm FDX22. (See “GlobalFoundries Chases Down a Different Semiconductor Rabbit Hole.”) In May, GF announced an RF meta platform called GF Connex that rolls together elements of the company’s RF SOI, FDX, SiGe, and FinFET semiconductor platforms to meet the varied communications needs of smart mobile and IoT devices and communications infrastructure equipment.
For its part, ST currently offers a 28nm FD-SOI process/platform. The 28nm node is currently the most cost-efficient process node in the industry, so there are a lot of economic benefits to staying with this node. However, technology inevitably marches on, and the Crolles joint announcement mentions an 18nm ST process technology. This appears to be the same 18nm FD-SOI process technology with embedded PCM (nonvolatile phase-change memory) that Orio Bellezza – President, Technology, Manufacturing, Quality and Supply Chain at ST – discussed during his STMicroelectronics Capital Markets Day presentation titled “Technology and Manufacturing” in May of this year.
The joint announcements by ST, GF, and CEA bolster FD-SOI’s position as a viable alternative to GAAFETs for the next few decades in specific applications, including applications in the automotive, IoT, and mobile markets. For these applications, it’s not the sheer number of transistors that’s important; it’s what those transistors can do.
For more information about the various semiconductor foundry platforms GF currently offers including the 22nm FD-SOI platform called FDX, see “GlobalFoundries Chases Down a Different Semiconductor Rabbit Hole.”

 

[LexLuther77]

Thanks wilzy. Yep it’s there but could also do it as a seperate announcement just like when Akida 1000 was done (my recall). Different ways to communicate good news etc and why have to read through a 8 page report. WBT consider tape outs as a seperate announcement (milestone) just so investors don’t miss it. All good, just different from my point of view only.

100% agree Pope

 

[Diogenese]

Know my last couple of posts banging on about FDSOI but I'm curious to understand the shift by BRN for AKD1500.

As suggested prev, possible input from potential / existing clients as an option / POC?

Another random thought....does 1500 use a little more power and as such shifting to FDSOI assists keeping low power as it's less hungry?

One other after reading the below, is if it's also strategic. With GF coming online in France in a couple years it gives Euro clients the capability / option of using them locally from a supply chain view increasing Akida access / footprint?

STMicroelectronics and GlobalFoundries Jointly Press on with FD-SOI in a New Fab Near Grenoble

STMicroelectronics (ST) and GlobalFoundries (GF) have just signed a memorandum of understanding to create a new, jointly operated 300mm semiconductor fab to be located alongside ST’s existing fab i…

www.eejournal.com

August 1, 2022

STMicroelectronics and GlobalFoundries Jointly Press on with FD-SOI in a New Fab Near Grenoble​

by Steven Leibson
STMicroelectronics (ST) and GlobalFoundries (GF) have just signed a memorandum of understanding to create a new, jointly operated 300mm semiconductor fab to be located alongside ST’s existing fab in Crolles, France. The new fab will support multiple semiconductor technologies and process nodes, including FD-SOI (fully depleted silicon on insulator). ST and GF expect that the fab will start producing chips in 2024 and will ramp to full capacity, producing as many as 620,000 300mm wafers per year, by 2026.
The Grenoble area in southeastern France, not far from the Italian border, has long been a hotbed of FD-SOI development. In many ways, FD-SOI is a lower-tech approach to realizing some of the benefits of FinFETs and gate-all-around FETs (GAAFETs) – including higher speed, lower power consumption, and less parametric variation on a chip from transistor to transistor thanks to the conduction channel being fully depleted (undoped). Less on-chip parametric variation means that IC designers can reduce the amount of design margin needed – for both supply voltage and timing – which improves the chip’s speed and lowers its power consumption by lowering the required operating voltage.
Dr. Chenming Hu and his team at the University of California, Berkeley, developed FinFETs way back in 1999 under a DARPA contract. DARPA cut that contract because it was clear that planar FETs would eventually run out of gas after their half-century run as they were scaled smaller and smaller. DARPA sought an alternative.
Small planar FETs suffer from short-channel leakage, which prevents the FET from turning off completely. The advantage that FinFETs have over planar FETs is that the FinFET architecture constructs a gate around three of the FET channel’s four sides. This arrangement allows the electric field from the gate to penetrate more deeply into the FET’s conduction channel, which reduces short-channel leakage and allows better control over the current through the channel.
Short-channel leakage increased in magnitude as planar FET dimensions shrunk, causing power consumption and heat-dissipation challenges to grow and forcing semiconductor makers to adopt FinFETs. Intel was the first commercial semiconductor company to adopt FinFETs for its 22nm process node back in 2011, more than a decade after FinFETs were first developed. FinFETs are currently used almost universally for chips made with 20nm process nodes or newer.
However, FinFETs are now running out of gas. Driving three sides of the FinFET transistor’s gate no longer achieves the desired speeds and low leakage currents. We must now drive all four sides of the FET gate to get a well-behaved transistor. Enter GAAFETs, which are already in production at Samsung’s fabs in that company’s 3nm process node. Intel and TSMC will also be using GAAFETs for their Intel 20A and N2 2nm nodes respectively. Samsung calls its GAAFETs “Multi-Bridge-Channel FETs” (MBCFETs); Intel calls them “RibbonFETs”; and TSMC calls them nanosheet GAAFETs. (See “Intel Welcomes You to the Angstrom Era” and “Moore’s Law: Not Dead Yet? Nope, Says Intel:, Behold Intel 4… and 3.”)
Like FinFETs, GAAFETs are 3D structures. Instead of fins, GAAFET conduction channels are built with undoped silicon nanowires, nanosheets, or ribbons that are so thin that they are essentially 2D structures, made with advanced process technologies such as atomic layer deposition (ALD). These nanoscale conduction channels are entirely encapsulated by the GAAFET’s gate structure.

​

The ultra-thin conduction channel of an FD-SOI FET does not suffer from the same leakage effects as a planar FET made in bulk silicon. Image credit: STMicroelectronics.
FD-SOI FETs have what is essentially a 2D conduction channel, created by bonding or otherwise applying a very thin, extremely uniform layer of silicon on top of a thin, grown silicon dioxide insulation layer. If the FD-SOI FET’s conduction channel is thin enough, the electric field from the transistor gate sitting on top of the conduction channel fully penetrates the channel, thus eliminating the need for a gate structure that surrounds the channel on all four sides, as is done with GAAFETs.
Except for the FD-SOI substrate, FD-SOI FETs are made in a similar manner and with the same equipment used to make planar FETs. The GAA structure is more complex and requires the use of expensive EUV lithography to create the small structures required. Like FinFETs and GAAFETs, FD-SOI FETs do not suffer from short-channel leakage problems, and they don’t require EUV lithography as do GAAFETs. So, you might call FD-SOI transistors “gate-almost-all-around FETs” (GAAAFETs). You might, but no one does.
By an interesting coincidence, the same UC Berkeley team – led by Dr. Chenming Hu – that developed the FinFET under a DARPA contract in 1999, simultaneously developed something very much akin to the FD-SOI FET architecture under the very same DARPA contract. Hu dubbed this second FET structure UTBSOI (Ultra Thin Body Silicon on Insulator).
FinFETs, GAAFETs, and UTBSOI FETs offer many benefits over planar MOSFETs:

• Better signal swing
• Less sensitivity to gate length and drain voltage
• No random dopant fluctuations because the FinFETs fins, the nanostructured conduction channels in GAAFETs, and the thin conduction channel in UTBSOI/FD-SOI FETs are all fully depleted – they’re not doped
• Higher on current with lower leakage
• Lower Vdd and lower leakage, therefore less power consumption

There are at least two important differences between FinFETs or GAAFETs and UTBSOI/FD-SOI FETs. First, it’s relatively easy to add back biasing beneath the channel of an FD-SOI FET, a capability that’s enabled by the bulk silicon substrate under the thin insulating layer on the wafer. Back biasing allows you to play with FET threshold voltages and to tweak performance and power consumption. If you decide to get really fancy, you can tweak individual FETs on the chip by using the silicon under each transistor as a second gate. There’s no easy way to add back biasing to FinFETs or GAAFETs. Second, you don’t get smaller transistors with FD-SOI relative to FinFETs or GAAFETs, so you don’t achieve the same transistor densities. That’s the flip side of not requiring expensive EUV lithography.
FD-SOI processing is still more expensive than conventional planar IC processing because it requires special FD-SOI wafers. It’s just not as expensive as the EUV lithography and other 3D processing techniques needed to make small FinFETs and GAAFETs. Conventional IC manufacturing uses bulk silicon wafers, which are much less expensive than FD-SOI wafers. The major supplier of FD-SOI wafers is Soitec in Bernin, which is literally just down the street from the STMicroelectronics Crolles fab complex north of Grenoble.

​

By coincidence, Soitec, GF, and ST, along with CEA (the French Alternative Energies and Atomic Energy Commission), announced a collaborative agreement earlier this year to jointly define the industry’s next generation roadmap for FD-SOI. In that announcement, CEA Chairman François Jacq said, “CEA has… a long history of deep R&D cooperation with… STMicroelectronics, Soitec and GlobalFoundries and has been very active in the initiatives led by the European Commission and Member States aiming to set up a complete ecosystem for FD-SOI going from material suppliers, design houses, EDA tools providers, fabless companies, and end users.” These are the elements that constitute an FD-SOI “platform.”
July’s ST/GF FD-SOI memorandum announcement also says, “ST and GF will receive significant financial support from the State of France for the new facility. This facility will strongly contribute to the objectives of the European Chips Act, including the goal of Europe reaching 20% of worldwide semiconductor production by 2030.” This statement was a European poke in the eye for the US government, which appeared to be dragging its heels on the country’s own CHIPS Act, much to the chagrin of companies such as Intel and TSMC. However, the US Senate and House of Representatives finally passed the bill last week and US President Joe Biden is expected to sign it into law this week.
It appears that France is going big on FD-SOI, which is not a bad strategy if you don’t plan to buy a $150 million EUV stepper or the next-generation $300 million “High NA” EUV stepper from ASML. FD-SOI confers many of the FinFET’s and GAAFET’s advantages on a far less expensive process node. GF already offers two FD-SOI process nodes or platforms called RF SOI and 22nm FDX22. (See “GlobalFoundries Chases Down a Different Semiconductor Rabbit Hole.”) In May, GF announced an RF meta platform called GF Connex that rolls together elements of the company’s RF SOI, FDX, SiGe, and FinFET semiconductor platforms to meet the varied communications needs of smart mobile and IoT devices and communications infrastructure equipment.
For its part, ST currently offers a 28nm FD-SOI process/platform. The 28nm node is currently the most cost-efficient process node in the industry, so there are a lot of economic benefits to staying with this node. However, technology inevitably marches on, and the Crolles joint announcement mentions an 18nm ST process technology. This appears to be the same 18nm FD-SOI process technology with embedded PCM (nonvolatile phase-change memory) that Orio Bellezza – President, Technology, Manufacturing, Quality and Supply Chain at ST – discussed during his STMicroelectronics Capital Markets Day presentation titled “Technology and Manufacturing” in May of this year.
The joint announcements by ST, GF, and CEA bolster FD-SOI’s position as a viable alternative to GAAFETs for the next few decades in specific applications, including applications in the automotive, IoT, and mobile markets. For these applications, it’s not the sheer number of transistors that’s important; it’s what those transistors can do.
For more information about the various semiconductor foundry platforms GF currently offers including the 22nm FD-SOI platform called FDX, see “GlobalFoundries Chases Down a Different Semiconductor Rabbit Hole.”

Hi fmf,

Re your random musings about 1500 using more power.

My guess is that LSTM requires extra memory and logic. Extra memory because of more stored data - more data means more data movements, so I'm inclined to agree that 1500 would use more power than Akida 1000.

However, compared to any other arrangement with equivalent capabilities, 1500 would win hands down.

The article @Townyj posted above discusses using FD-SOI in automotive applications.

We've also seen reference to DoD involvement with GlobalFoundries, possibly driven by US's need to disengage with China and build in-house tech, and somewhere nearby is a reference to FinFETs radiation robustness.

So there are several potential drives (NASA comes to mind), more than mentioned here, all of which could have played a part in BrainChip selecting GF, but I would think the military-industrial complex is a significant one.

I reaaaaally like this part..

View attachment 28258

 

[Taproot]

From a quick skim I couldn't see that TSMC uses FDSOI tech? Happy to be corrected.

Maybe this is part of the GF approach by BRN...additional tech / flexibility options?

Bit about FDSOI.

A Close Look at Major Microelectronics Challenges

To address the shortage of semi-conductors which continues to impact many sectors, including the automotive industry, and meet the growing need for electronic components, its production capacities must significantly increase.

www.leti-cea.com

Excerpt from mid 2022.

Where does CEA-Leti stand with regard to the European Chips Act?​

CEA-Leti supports the idea of creating three major drivers. One of the major drivers we have proposed would involve working on a technology that emerged in Europe, in our institute, FD-SOI. It is used to produce transistors, small switches that are indispensable to integrated electronic circuits and constituting the smallest processor value unit. Because it provides optimized energy consumption (with an energy saving of 30% compared to other technologies), FD-SOI is extremely interesting for 'embedded' markets, meaning electronics found in connected objects, autonomous cars, nomadic electronics, etc. Millions of connected loudspeakers or GPS microchips are now fitted with it. FD-SOI is also fueling smartphones, such as Google's latest pixel 6 Pro. Industrialized by STMicroelectronics, it is also sold by big companies such as Samsung and GlobalFoundries. FD-SOI is currently produced in 28 nm and 22 nm and will soon be available in 18 nm. To further improve the performance and energy efficiency of FD-SOI, the goal is now to move toward new electronic engineering technology, with ever-smaller 10-nanometer nodes that will meet low consumption market needs in 5 to 7 years. This miniaturization involves a major technological leap. Secondly (by 2026–2030), we will be focusing on GAA technology (Gate-All-Around, including a gate around the conduction channel) with nodes typically around 5 nm. One could say we've invented this technology (first publications in 2006 and first patent filed by CEA-Leti), which will constitute a breakthrough. The second major driver, supported by Imec, the Flemish Interuniversity Microelectronics Center, will be devoted to advanced generation FinFET chips — with nodes equal or less than 2 nm — which use the most advanced lithography techniques (Extreme UV) with equipment that will later be produced by Dutch world leader ASML. The third major driver, generated by the Fraunhofer Institute, in Germany, involves assembly and packaging, which will bring challenges in years to come.

Naturally, we will all need to work together, and we are in regular contact with both Imec and the Fraunhofer.


Also worth a skim through from a few years back.

FD-SOI Adoption Expands

FD-SOI Adoption Expands Technology shifts direction after years of competing directly with CMOS at advanced nodes.

semiengineering.com

Foundries Prepare For Battle At 22nm​

from 2018

But choosing one 22nm technology from a given foundry may be far different than 22nm at a different foundry. There are three different versions of 22nm being rolled out by different foundries:

• TSMC and UMC are developing a 22nm planar bulk CMOS process.
• GlobalFoundries is gearing up a 22nm planar FD-SOI technology.
• Intel is pushing a low-power 22nm finFET technology.

Foundries Prepare For Battle At 22nm

Foundries Prepare For Battle At 22nm Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where do chipmakers go after 28nm?

semiengineering.com

This article may answer a few questions in the the context of today's press release.

"The AKD1500 reference chip using GlobalFoundries’ very low-leakage FD SOI platform, showcases the possibilities for intelligent sensors in edge AI.” Anil Mankar

 

[Newk R]

If the SP is influenced by cold hard cash influxes then it will shape my investment strategy. If the SP is influenced by the date of a tape out then it will not reflect in m y strategy. Simples. So give me solid revenue figures and I know I'm onto something.

 

[GazDix]

Thank you so much @BienSuerte for sharing Tony's reply.
In a seperate discussion I had with @BaconLover earlier I also remembered Akida 1000 having a seperate announcement, so you are spot on @The Pope.
The precedent for reporting has changed under our new CEO as Tony has hinted. I would also predict that Ken Scarince had input too about the change after all the crap after speeding tickets, the patents that were late (but in a different time zone) and Brainchip obviously being targeted by the AFR, HC just as our new CEO joined us in November 2021.

Not only does WBT announce taping/successful fabs etc. but many other companies thrive on this like AXE (Archer Materials) and 4DS who only update tech improvements. So Brainchip can easily file these announcements with the ASX. There is being careful, but then being beyond paranoid (or is it strategic...) that we have stopped announcing anything that won't directly involve a revenue stream.

If I was paranoid, after being targeted by the ASX and the mainstream financial media in Australia who are not tech-savvy, or really paranoid that they know we will be gigantic like the next BHP division Blue Chip on the ASX and 'they' will gather all forces to collect shares and disrupt the leadership of my company, I would also be proper careful and conservative and take a very cautious approach.

Anyway, price is price. Business is business and business is looking up after today. Price always follows but not always in the way we hope.

 

[Taproot]

Foundries Prepare For Battle At 22nm​

from 2018

But choosing one 22nm technology from a given foundry may be far different than 22nm at a different foundry. There are three different versions of 22nm being rolled out by different foundries:

• TSMC and UMC are developing a 22nm planar bulk CMOS process.
• GlobalFoundries is gearing up a 22nm planar FD-SOI technology.
• Intel is pushing a low-power 22nm finFET technology.

Foundries Prepare For Battle At 22nm

Foundries Prepare For Battle At 22nm Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where do chipmakers go after 28nm?

semiengineering.com

This article may answer a few questions in the the context of today's press release.

"The AKD1500 reference chip using GlobalFoundries’ very low-leakage FD SOI platform, showcases the possibilities for intelligent sensors in edge AI.” Anil Mankar

An extract from the article.

FD-SOI
GlobalFoundries was the first player to enter the 22nm race. Three years ago the company introduced a 22nm FD-SOI technology. For some time, Samsung has offered 28nm FD-SOI with an 18nm version in the works.

In addition, GlobalFoundries is developing a 12nm planar version of FD-SOI, which is expected to appear in 2022. Generally, 22nm or 18nm FD-SOI doesn’t compete with 16nm/14nm finFETs, and they serve different markets with little overlap.

FD-SOI uses a specialized SOI wafer, which integrates a thin insulating layer (20 to 25nm thick) in the substrate. This layer isolates the transistor from the substrate, thereby blocking the leakage in the device.

FD-SOI also is based on a planar, fully depleted architecture. “This essentially eliminates the random dopant fluctuation, providing superior mismatch and electrostatics to improve sub-threshold slope,” GlobalFoundries’ Schaeffer said.

GlobalFoundries’ 22nm FD-SOI technology, called 22FDX, incorporates high-k/metal-gate with silicon-germanium in the channel. It provides 30% higher performance and 45% lower power compared to 28nm. It was production-qualified in early 2017.

Recently, GlobalFoundries added more capabilities to the mix. “Sub-6GHz RF, mmWave, ultra-low leakage and ultra-low power extensions have all been qualified,” Schaeffer said.

What makes FD-SOI attractive are two features—low-power and body bias. It enables drive currents of 910μA/μm (856μA/μm) at 0.8 volts, with voltage operations down to 0.4 volts.

“Body bias is the ability to fully control the threshold voltage (Vth) of the transistors dynamically by polarizing the back gate of the transistor. Vth—which was a parameter determinable only by process through complex doping techniques—is now programmable dynamically through software,” said Manuel Sellier, product marketing manager at Soitec. “Designers can use this feature to dynamically manage the leakage in their circuit, and also to compensate static (process) and dynamic variations (temperature, voltage, and aging) efficiently. The result is a 4X to 7X energy efficiency gain at ultra-low power.”

FD-SOI also supports forward body biasing. When polarization of the substrate is positive, the transistor can be switched faster, according to STMicroelectronics.

FD-SOI, however, has three drawbacks—cost, ecosystem and adoption. For years, FD-SOI has had limited adoption. Intel, TSMC, UMC and others have never adopted FD-SOI, saying bulk CMOS enables high-performance devices at better costs. For example, an SOI wafer sells from $370 to $400 each, compared to $100 to $120 for a bulk CMOS wafer.

But FD-SOI does have a lower mask count, which compensates for the wafer cost. FD-SOI has 22 to 24 mask steps, while a comparable bulk CMOS process has 27 to 29 mask steps, according to IBS.

FD-SOI is closing the gap, too. “We are now looking at what we view as the limit of bulk CMOS,” IBS’ Jones said. “Transistor costs for 22nm FD-SOI are within 5% of the transistor costs for 22nm HKMG (high-k/metal-gate). 22nm FD SOI gives 30% to 50% lower power consumption compared to 22nm HKMG, which is important for wearable and IoT devices.”

The FD-SOI community, however, lags in terms of the EDA/IP ecosystem. “The IP ecosystem for 22nm FD-SOI is strengthening, but 22nm HKMG bulk CMOS has a broader IP ecosystem,” Jones said.

The tide is turning. Cadence, Mentor and Synopsys have been certified for various EDA tools for GlobalFoundries’ FD-SOI technology.

“There are some unique capabilities for RF, for example, with integrated FD-SOI, which are very hard to equal in other ways,” said Wally Rhines, president and CEO of Mentor.

FD-SOI has other advantages. “While the finFET gives you near zero leakage, you still have dynamic power. One of the advantages of FD-SOI is dynamic power. If you can reduce the voltage from one volt down to 0.6, that’s a 65% reduction in power. FD-SOI has some advantages in being able to dynamically alter the power versus the performance balance,” Rhines said.

 

[Kachoo]

There hasn't been much talk about some of the finer points.
One I particularly like,
We expect our next
reference chips (plural) to be delivered in Q2 of this year.

Well maybe it's just that they will tape more then one chip. I would not read too much in to the wording. If I'm wrong then it's better for my pocket lol.

 

[Kachoo]

After reading the release again and checking in on past news I'm satisfied with the companies progress...

Taping out 1500 is excellent news. You know the more foundries that produce our chip and have our IP will really benifit us in the long run.

Think of it this way some customers prefer to use GL not TSCS and so forth. We will be hitting more customers potentially.

1.2 million receipts from customers is okay in my books. I look forward to February's year end report.

 

[Deleted member 118]

Thank you, for not posting cooked diatribe. Forum has really gone downhill last few days.

 

[Rise from the ashes]

So Rise, as @Bravo piles on the scaling-mountain-of-dots and @TECH outlines the logical timeframes, it has triggered your derisked-threshold?

Therefore, you activate a Binary Step Function to buy some more BRN. Very logical!!!
(Dio mentioned Step Functions and got me curious.)

https://towardsdatascience.com/getting-to-know-activation-functions-in-neural-networks-125405b67428

View attachment 28200

BRN has been de-risked for me for sometime, share price fluctuations are out of my control it's all about trying to pick a price I'm happy with topping up and imo the prices we are seeing are going to be dirt cheap compared to future price.

 

[ENZee2]

Attention all whining and whinging, lazy people, who are still holding mommies hand.
If you haven't registered on the companies website for email updates, then you don't deserve to know what's going on.
Don't be so, FFFing pathetic.

Here Here Post of the day

 

[Rise from the ashes]

Attention all whining and whinging, lazy people, who are still holding mommies hand.
If you haven't registered on the companies website for email updates, then you don't deserve to know what's going on.
Don't be so, FFFing pathetic.

Agreed WH, A few holder who I got in have previously stated 'whinge , whinge nothing going on with BRN " I've told them to sign up to company website also sub to brn YouTube channel also to sign up here. One is not too bad but the other I feel like slamming my elbow straight into his face, such a f dick.
Edit... Oh and of course when asked if the price was over a buck something a piece they would not give a flying shag with the lack of official news.
Edit 2 no one was harmed in the construction of this post.

 

[thelittleshort]

An extract from the article.

FD-SOI
GlobalFoundries was the first player to enter the 22nm race. Three years ago the company introduced a 22nm FD-SOI technology. For some time, Samsung has offered 28nm FD-SOI with an 18nm version in the works.

In addition, GlobalFoundries is developing a 12nm planar version of FD-SOI, which is expected to appear in 2022. Generally, 22nm or 18nm FD-SOI doesn’t compete with 16nm/14nm finFETs, and they serve different markets with little overlap.

FD-SOI uses a specialized SOI wafer, which integrates a thin insulating layer (20 to 25nm thick) in the substrate. This layer isolates the transistor from the substrate, thereby blocking the leakage in the device.

FD-SOI also is based on a planar, fully depleted architecture. “This essentially eliminates the random dopant fluctuation, providing superior mismatch and electrostatics to improve sub-threshold slope,” GlobalFoundries’ Schaeffer said.

GlobalFoundries’ 22nm FD-SOI technology, called 22FDX, incorporates high-k/metal-gate with silicon-germanium in the channel. It provides 30% higher performance and 45% lower power compared to 28nm. It was production-qualified in early 2017.

Recently, GlobalFoundries added more capabilities to the mix. “Sub-6GHz RF, mmWave, ultra-low leakage and ultra-low power extensions have all been qualified,” Schaeffer said.

What makes FD-SOI attractive are two features—low-power and body bias. It enables drive currents of 910μA/μm (856μA/μm) at 0.8 volts, with voltage operations down to 0.4 volts.

“Body bias is the ability to fully control the threshold voltage (Vth) of the transistors dynamically by polarizing the back gate of the transistor. Vth—which was a parameter determinable only by process through complex doping techniques—is now programmable dynamically through software,” said Manuel Sellier, product marketing manager at Soitec. “Designers can use this feature to dynamically manage the leakage in their circuit, and also to compensate static (process) and dynamic variations (temperature, voltage, and aging) efficiently. The result is a 4X to 7X energy efficiency gain at ultra-low power.”

FD-SOI also supports forward body biasing. When polarization of the substrate is positive, the transistor can be switched faster, according to STMicroelectronics.

FD-SOI, however, has three drawbacks—cost, ecosystem and adoption. For years, FD-SOI has had limited adoption. Intel, TSMC, UMC and others have never adopted FD-SOI, saying bulk CMOS enables high-performance devices at better costs. For example, an SOI wafer sells from $370 to $400 each, compared to $100 to $120 for a bulk CMOS wafer.

But FD-SOI does have a lower mask count, which compensates for the wafer cost. FD-SOI has 22 to 24 mask steps, while a comparable bulk CMOS process has 27 to 29 mask steps, according to IBS.

FD-SOI is closing the gap, too. “We are now looking at what we view as the limit of bulk CMOS,” IBS’ Jones said. “Transistor costs for 22nm FD-SOI are within 5% of the transistor costs for 22nm HKMG (high-k/metal-gate). 22nm FD SOI gives 30% to 50% lower power consumption compared to 22nm HKMG, which is important for wearable and IoT devices.”

The FD-SOI community, however, lags in terms of the EDA/IP ecosystem. “The IP ecosystem for 22nm FD-SOI is strengthening, but 22nm HKMG bulk CMOS has a broader IP ecosystem,” Jones said.

The tide is turning. Cadence, Mentor and Synopsys have been certified for various EDA tools for GlobalFoundries’ FD-SOI technology.

“There are some unique capabilities for RF, for example, with integrated FD-SOI, which are very hard to equal in other ways,” said Wally Rhines, president and CEO of Mentor.

FD-SOI has other advantages. “While the finFET gives you near zero leakage, you still have dynamic power. One of the advantages of FD-SOI is dynamic power. If you can reduce the voltage from one volt down to 0.6, that’s a 65% reduction in power. FD-SOI has some advantages in being able to dynamically alter the power versus the performance balance,” Rhines said.

My vote is for satellites

FDX™ FD-SOI | GlobalFoundries

Purpose-built for connected intelligence at the edge

gf.com

 

[Taproot]

This from August 21
Looks like AKD500 will be next

What does the road ahead look like for Akida?
AKD1000 is only the beginning of what the company expects to be a robust product portfolio (Figure 33): – AKD500: BRN is in the planning stages for AKD500, which is a low-cost version of the AKD1000, for the consumer products market. – AKD1500: BRN is also in the process of developing and prototyping AKD1500, which will have additional features to execute Long Short-Term Memory (LSTM) and Transformer networks. LSTM is a form of recurrent neural network which can learn order dependence in sequence prediction problems. It finds applications in machine translation and speech recognition. Transformer networks, on the other hand, find their applications in natural language processing (NLP) due to their ability to resolve the vanishing gradient problem – the time for which the memory is retained by the network, which is critical in order to process lengthy texts. – AKD2000: It is the optimised version of AKD1500 and the company has already started work on a prototype at its lab in Perth.

 

[Rise from the ashes]

Am I mistaken but I do recall that these different versions of chips can all be combined at a later stage?

 

[Getupthere]

In electronics and photonics design, tape-out or tapeout is the final result of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing. The tapeout is specifically the point at which the graphic for the photomask of the circuit is sent to the fabrication facility.

 

[cassip]

BRN

 

[Cirat]

BRN

Always loved the clean, crisp and visually standout nature of our new website as well as the kite which they use in marketing material such as the recently released White Paper.
The kite reminds me of a song (decades ago) which says it all about Brainchip:

"Let's go fly a kite
Up to the highest height
Let's go fly a kite
And send it soaring
Up through the atmosphere
Up where the air is clear
Oh, let's go fly a kite"

Nothing more to say

 

[White Horse]

I think what happened was we have had a huge runs over the last couple of years and retraced well too.
We have had a few Anns like NASA, Ford etc which caused massive runs after BRN was asked to ''please explain''.
We have plenty of organisations such as AFR, Motley Fools etc., their friends, other hedge funds, instos... who all would ask for a ''fair and reasonable'' market by reporting these to ASX (I say this because I know there are reporters on AFR who specialise in this sort of reporting and have listened to their side of story myself).
Unfortunately retails are not in their club so our reports will be in the bin straight away.

I believe WBT isn't having such huge volatility and is possibly flying under the radar already so they wouldn't have an issue. Their SOI is comparatively lower, at around 173 million and out of that around 34 million is with top 20. Not much room for the big guys to play around.

These are only my opinion only, dyor.



Exactly

Hi BL,
It's not "exactly", because I was not supporting an argument for more disclosure.
I was pointing out that Weebit are going the same FAB route as us with 22nm FD-SOI.
Nothing to do with the argument you and others have been flogging to death all day.
If you and others can't get you mind around the companies disclosure policy, you should sell
and buy into these other companies of which you are so enamored.
Actually , not just today, but what seems like forever.

Regards
WH