BRN Discussion Ongoing

Frangipani

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Found a brand new University of Sydney PhD thesis, which is highly likely related to the GitHub “Akida Seizure” repository that one of the two thesis supervisors, Omid Kavehei, had set up under the GitHub name NeuroSyd just over two months ago (which seems to have disappeared since or has possibly been renamed?), spotted by @Fullmoonfever at the time. 👆🏻



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University of Sydney PhD candidate Andre Zainal, who has a B.Eng. (Biomedical) & B.MedSci background, embarked on his Research PhD in Biomedical Engineering just a week ago, “researching AI-driven neuromorphic hardware for early seizure detection”.
The title of his thesis is “Optimizing Training Algorithms for Neuromorphic Hardware: Enhancing In-Memory Computing with FPGA and Akida Neural Processors for Epileptic Seizure Detection”.

Akida doesn’t have “in-memory-computing”, though? 🤔




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Andre Zainal’s first PhD supervisor Omid Kavehei has been conducting epilepsy research for years:


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(…)


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More on Andre Zainal’s two PhD supervisors:

Principal supervisor Omid Kavehei is not only Professor at University of Sydney’s School of Biomedical Engineering, but also Director and Founder of BrainConnect (https://brainconnect.com.au/), the stealth startup “developing novel solutions in long-term interfacing with the brain and body”, where co-supervisor Duy Nhan Truong works as Engineering Lead.

Prior to filling that position, Duy Nhan Truong also used to be at University of Sydney, initially as a PhD student in Electrical and Electronics Engineering (transferred from RMIT University in 2018, PhD thesis completed in 2020, titled “Epileptic Seizure Detection and Forecasting Ecosystems”, principal supervisor: Omid Kavehei; https://ses.library.usyd.edu.au/bitstream/handle/2123/21932/truong_nd_thesis.pdf?) and later as a postdoc.



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Frangipani

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There is a 2 min movie talking up the collaboration but it want copy across so have to view it in the LinkedIn link!


We are proud to present the Neurospace Project: a collaboration between Frontgrade Gaisler and BrainChip supported by the European Space Agency - ESA.

At its center: GR801, our first neuromorphic AI solution for space.
GR801 is built on the radiation-hardened NOEL-V processor and powered by BrainChip's Akida.

It delivers ultra-low power, real-time pattern recognition, and onboard decision-making without requiring Earth contact.
This is more than a milestone.
It's a paradigm shift for AI at the edge of space exploration.

Learn more: https://lnkd.in/dMq9sxkp
And https://lnkd.in/dSx8_mTQ
Also available on YouTube: https://lnkd.in/dC6_aWR2

#NeuromorphicAI #SpaceTech


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Frangipani

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Arijit Mukherjee is already busy co-organising another Edge AI workshop that will also touch on neuromorphic computing. It is scheduled for 8 October and will be co-located with AIMLSys 2025 in Bangalore:

“EDGE-X 2025: Reimagining edge intelligence with low-power, high-efficiency AI systems”.


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EDGE-X

The EDGE-X 2025 workshop, part of the Fifth International AI-ML Systems Conference (AIMLSys 2025), aims to address the critical challenges and opportunities in nextgeneration edge computing. As intelligent systems expand into diverse environments—from IoT sensors to autonomous devices—traditional applications, architectures, and methodologies face new limits. EDGE-X explores innovative solutions across various domains, including on-device learning and inferencing, ML/DL optimization approaches to achieve efficiency in memory/latency/power, hardware-software co-optimization, and emerging beyond von Neumann paradigms including but not limited to neuromorphic, in-memory, photonic, and spintronic computing. The workshop seeks to unite researchers, engineers, and architects to share ideas and breakthroughs in devices, architectures, algorithms, tools and methodologies that redefine performance and efficiency for edge computing.

Topics of Interest (including but not limited to the following):
We solicit submissions describing original and unpublished results focussed on leveraging software agents for software engineering tasks. Topics of interest include but are not limited to:

1.Ultra-Efficient Machine Learning
    • TinyML, binary/ternary neural networks, federated learning
    • Model pruning, compression, quantization, and edge-training
2.Hardware-Software Co-Design
    • RISC-V custom extensions for edge AI
    • Non-von-Neumann accelerators (e.g., in-memory compute, FPGAs
3.Beyond CMOS & von Neumann Paradigms
    • Neuromorphic computing (spiking networks, event-based sensing)
    • In-memory/compute architectures (memristors, ReRAM)
    • Photonic integrated circuits for low-power signal processing
    • Spintronic logic/memory and quantum-inspired devices
4.System-Level Innovations
    • Near-/sub-threshold computing
    • Power-aware OS/runtime frameworks
    • Approximate computing for error-tolerant workloads
5.Tools & Methodologies
    • Simulators for emerging edge devices (photonic, spintronic)
    • Energy-accuracy trade-off optimization
    • Benchmarks for edge heterogeneous platforms
6.Use Cases & Deployment Challenges
    • Self-powered/swarm systems, ruggedized edge AI
    • Privacy/security for distributed intelligence
    • Sustainability and lifecycle management
  • Program Committee
  • Arijit Mukherjee, Principal Scientist, TCS Research
  • Udayan Ganguly, Professor, IIT Bombay

Cecilia Pisano from Nurjana Technologies has repeatedly liked BrainChip posts on LinkedIn, and hence her Sardinia-based company has been mentioned by several forum members as potentially playing with Akida:

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And here’s the proof that it was indeed worth keeping an eye on Nurjana Tech :


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Frangipani

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Cecilia Pisano from Nurjana Technologies has repeatedly liked BrainChip posts on LinkedIn, and hence her Sardinia-based company has been mentioned by several forum members as potentially playing with Akida:

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And here’s the proof that it was indeed worth keeping an eye on Nurjana Tech :


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Some interesting recent posts by Cecilia Pisano about two projects that Nurjana Technologies is involved in - as a consortium member in the STAALION* project, co-funded by the European Defense Fund (EDF) resp. as a project coordinator and lead in the AIRYS** project, supported by the European Defence Agency (EDA). AIRYS was officially launched last month, but has been in the making for over a year:


*STAALION = “Space Threats Analysis based on Automated reaL-time In-situ capabilities and Onboard processing decentralized Network”

** AIRYS = AI-Based Rapid Prototyping of a Stealth Drone



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TheDrooben

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manny100

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It's all in front of us.
What a great time to get in on the ground floor for expected market growth.
i asked AI:
" What is the total global market size thresholds for non existent, small, medium and large neuromorphic AI at the Edge chip markets"
Response:

Global Market Size Thresholds for Neuromorphic AI-at-the-Edge Chips​

To gauge where the neuromorphic AI-at-the-edge chip market stands today, you can use these rough annual revenue bands:


CategoryAnnual Global Revenue
Non-existentBelow USD 10 million
SmallUSD 10 million – 1 billion
MediumUSD 1 billion – 10 billion
LargeAbove USD 10 billion
Yole had the total market at $28 mill in 2024 - tiny - practically non existent. They have it growing to $822 mill by 2029 and $8352m by 2034.
By 2034 the market is still small but has had exponential growth with a huge runway in front of us. BRN's stated aim is to be in the top 2 or 3 leaders of a large Neuromorphic AI at the Edge chip market. We are already past the 'chip' only stage as we have our TENNs software and there will be more of that.
It's not often a chance to get in on the ground floor of an industry set for huge growth.
Sean at the Pitt Street conference a couple of months ago that the industry will make the Industrial and Information revolution look like nothing (2.20 mark - see link). Check the video out.
Yole Group - Follow the latest trend news in the Semiconductor Industry
Bing Videos
Clealry it's all in front of us.
 
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manny100

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Pinched from FF on the crapper.

Cecilia Pisano​

Premium member
R&D Lead Engineer/Project Coordinator @ Nurjana Technologies | AI, Space situational awareness, Autonomous UAVs, Optical payloads | PhD in Industrial Engineering
University of LimerickNurjana Technologies
Italy371 connections
Reimagining? We have been applying Brainchip Akida to real use cases for more than 1 year in my company
https://www.linkedin.com/in/cecilia...=feed-detail_comments-list_comment_actor-name
My comment - Appear to be another smaller company like Bascom Hunter seeing the huge growth potential of Brainchip and recognizing that this is their path to huge growth as well.
For proof of this strategy see below quote from the " Department of the Navy SBIR/STTR Transition Program" document. Link also attached.
Navy STP Workspace 2.0
Company Objectives: Bascom Hunter intends to lead the market with this technology, marrying it with our similar advances in neuromorphic photonics and our advanced RF systems designs; creating a new class of “snap-in” neuromorphic processors designed for the U.S. Armed Services and Intelligence Community.
 
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“Our current demo utilizes Intel x86 in conjunction with Aether Core LLM for showcasing our platform. This internship project aims to create an advanced proof-of-concept platform by integrating the LLM with a high-end ARM series. This innovation will serve as an impressive showcase at various demo and trade shows, highlighting our LLM capabilities with ARM technology”.

Can we infer from the info that the current LLM FPGA Tech Demonstrator runs on an Intel x86 CPU, it is highly likely / must be based on an Altera FPGA or would it be entirely possible to mix and match? I have no idea…


Evening @Frangipani, thanks that's interesting.
I'm not totally sure yet what to conclude from this job ad. As far as I know (and I might be totally wrong here) an Intel/Altera FPGA and x86 architecture initially have nothing to do with each other. So I do not take the mention of the x86-based system as an indication of an Altera FPGA, but it could be.


I probably would interpret this excerpt as:

Current state:
Our model/demo is currently running on an Intel x86 CPU.

Goal (of internship):
We want you to combine "a Raspberry Pi [...] with a custom FPGA-based hardware accelerator".


The aspects I'm less sure about how to interpret them are:

"a custom FPGA-based hardware accelerator"
Does this mean a custom accelerator using an off-the-shelf FPGA?

"integrating the LLM with a high-end ARM series"
"High-End" like a Raspberry Pi (ARM) CPU in comparison to a less beefy/powerfull MCU?
 
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